The present invention relates to a method for correcting an error in the data read out from a memory unit.
Generally, when data is written into a memory unit, redundancy bits are added to the data bits to be written and the data bits having a redundancy bits are then written, and a bit error in the data which was read out of the memory unit is detected or corrected on the basis of the redundancy bits.
In many cases, the added redundancy bits (i.e., check bits) can correct a single bit error and cannot correct a double or more bit error but can detect the presence of the double or more bit error. Therefore, an explanation will be made hereinbelow on the assumption of such a case. However, the present invention is not limited to only the above case.
FIG. 3 is a block diagram of a conventional method. In the diagram, reference numerals 1, 2, 3, 4, 5 and 6 denote a memory unit, a read data latch, a check code latch, a detecting circuit, a correcting circuit and a read data buffer, respectively.
Where the memory unit 1 is constructed with, for example, an conventional 64K Bytes Dynamic RAM, the read data latch 2 and the check code latch 3 are constructed with F373 produced by Fairchild Industries, Inc., the read data buffer 6 is constructed with F374 produced by Fairchild Industries, Inc. and the detecting circuit 4 and the correcting circuit 5 are constructed with Am2960, in which the circuits 4 and 5 are implemented together, produced by Advanced Micro Devices, Inc. (AMD).
The operation will now be described. A check code together with data has previously been written in the memory unit 1. The data portion in the content which was read out of the memory unit 1 is temporarily stored into the read data latch 2, while the check code portion is temporarily stored into the check code latch 3.
The contents of the read data latch 2 and of the check code latch 3 are checked by the detecting circuit 4 to thereby determine whether a bit error exists or not. If no error is detected, the content of the read data latch 2 is written into the read data buffer 6. If a bit error is detected by the detecting circuit 4 and it is decided that this bit error is correctable, the information indicative of the position of the error bit is outputted from the detecting circuit 4. The data whose bit error was corrected by the correcting circuit 5 is produced and this correct data is written into the read data buffer 6.
In this case, according to the conventional method, even when a bit error exists in the content of the check code latch 3 and no error is included in the content of the read data latch 2, the detecting circuit 4 regards that the data has a bit error and performs the processes, so that the data is written into the read data buffer 6 through the correcting circuit 5. Namely, in spite of the fact that there is no need to correct the content of the read data latch 2, it is transmitted through the correcting circuit 5 and then written into the read data buffer 6. On the other hand, if an uncorrectable bit error is detected by the detecting circuit 4, an error signal is outputted and the processing routine is terminated as an abnormal termination.
FIG. 4 is a flowchart of the operation of the system of FIG. 3. Numerals 40 and 41 represent respective processing steps.
As described above, according to the conventional method, even when no error bit exists in the data, if an error is detected in the check bits, the vain operation such that the data is outputted through the correcting circuit is executed and at the same time, there is a problem such that the data corrected by the correcting circuit is outputted without being rechecked.